Examples of using Clock cycle in English and their translations into Indonesian
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Colloquial
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Ecclesiastic
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Computer
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Ecclesiastic
including Tukwila execute up to six instructions per clock cycle.
which means that two transfers happen per clock cycle.
timing is described by clock cycle counts separated by hyphens.
To be specific, it is able to process 40 percent more instructions per clock cycle- this is the‘40% More IPC' in the slide below.
Single Data Rate means that SDR SDRAM can only read/write one time in a clock cycle.
allowing two independent registers to be accessed in one single instruction executed in one clock cycle.
An instruction pipeline is said to be fully pipelined if it can accept a new instruction every clock cycle.
This allows for multiple instruction streams, which means that more than one instruction can complete during each clock cycle.
was the first commercially available microprocessor capable of executing two instructions for every clock cycle.
permitting the codes to represent a greater volume of information per clock cycle.
aiming to execute instructions at a rate of almost one instruction per clock cycle.
The two factors combine to require a total of four data transfers per internal clock cycle.
It can also enable computers to crunch twice the data per clock cycle, which can dramatically speed up numeric calculations
which performs I/O transactions on both rising and falling edges of the clock cycle- recover its position of graphics memory of choice during the following year.
64-bit operations in each clock cycle.
Like DDR, DDR2 transfers data twice per clock cycle but DDR2 runs the internal clock at half the speed of the data bus which gives a total of four data transfers per internal clock cycle making it twice as fast as DDR.
they get more instructions completed per clock cycle.
which translates into about 18.4 instructions per clock cycle per second.
controlled by one unifying clock cycle.
which get more instructions completed per clock cycle.