It used"AOS" multiprocessing operating system for basic software. The microprogramming system was used for the central processing unit(CPU), and, combined with the use of LSI and MSI, this made the CPU extremely simple compared to the hard-wired logic system.
At that time, the price was ¥3.6 million for the central processing unit and 4K words of built-in magnetic core main memory, so it was called a $10,000 computer(exchange rate at that time: $1=\360), and was acclaimed for its high cost performance.
In addition to full on-chip encryption along the entire data path(CPUs, EEPROM, Flash, ROM and RAM, caches and buses), Infineon's security chips with“Integrity Guard” have two central processing units(CPUs) and a sophisticated error detection system.
The images captured from these cameras are sent to a central processing unit(for lack of a better term, not knowing exactly what it is), which does the real work of quickly and accurately identifying different people in the store and objects being picked up or held.
As logic ICs, the system used ECL with an average of 2 nanoseconds per gate in the central processing unit of the System 500, and TTL with an average of 5 nanoseconds per gate in the S300, S400 and S500. In the main memory unit, the S500 used 4K RAM, and the S300 and S400 used 1K RAM.
In particular, in this example, one or more central processing systems 10(two shown in this example for clarity purposes only) are provided at a base station 1, which is coupled via a communications network, such as the Internet 2, and/or a number of local area networks(LANs) 4, to a number of end stations 3.
HITAC3030-Computer Museum The HITAC 3030 was computer system designed specifically for real-time information processing and to serve as the central processing unit for the MARS-101 seat reservation system operated by the Japanese National Railways(today JR). The computer's core memory had a capacity of 4,096 words(with a cycling time of 10 microseconds; each word was 40 bits long) and each word had two instructions using a paired-order architecture.
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