영어에서 Instruction set 을 사용하는 예와 한국어로 번역
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IBM POWER- POWER is a RISC instruction set architecture designed by IBM.
Y MCSÉ 51 Controller Compatible Instruction Set.
The modern ARMv8 instruction set was designed for a 64-bit architecture.
Appraise an instruction set architecture;
The instruction set architecture.
Packed instruction set 143 includes instructions for performing embodiments of the invention and other packed instructions. .
Implement nearly identical versions of the x86 instruction set(with some extensions that have been added with newer versions), but have different internal designs.
HT48F50E HT48F50E is an 8-bit high-performance compact instruction set microcontroller designed for economical multiple.
The processors 16A-16B may implement any instruction set architecture, and may be configured to execute instructions defined in that instruction set architecture.
For example, the processor 510 may be a CISC(Complex Instruction Set Computers) processor, a RISC(Reduced Instruction Set Computer) processor, or a MISC(Minimal Instruction Set Computer) processor.
The OVF standard is not tied to any particular hypervisor or instruction set architecture.
Instruction Set Extensions are additional instructions which can increase performance when the same operations are performed on multiple data objects.
The cores 502A-N may be homogenous or heterogeneous in terms of architecture and/or instruction set.
On other platforms, this type of instruction is known as Halt and Catch Fire. hsc instruction, MIPS-X Instruction Set and Programmer's Manual, pp. 65.
code instrumentation, instruction set simulation, operating system hooks,
The general format of at least one instruction set(which corresponds generally with format 360 and/or format 370) is illustrated generically by the following.
The ICL 2900 Series provided a 128-bit accumulator, and its instruction set included 128-bit floating-point and packed decimal arithmetic.
This is the default option for targets that do not support the ARM instruction set.
The instruction set also has a substantial body of supporting software, which fixes a usual weakness of new instruction sets. .
The GCN instruction set has been developed specifically for GPUs(and GPGPU) and, for example, has no micro-operation for division.