时钟周期 in English translation

• clock cycle
• clock cycles
• clock period

Examples of using 时钟周期 in Chinese and their translations into English

在经典8051结构中，每次读取需要6个时钟周期，使得执行指令需要12、24或者48个时钟周期。
In the classic 8051 architecture, each fetch requires 6 clock cycles, forcing instructions to execute in 12, 24 or 48 clock cycles.

然而，他们的设计可以让电路可以迅速转变且重新配置，在每个时钟周期内完成特定的数字功能。
Our design allows the circuit to be rapidly morphed and reconfigured to perform a desired digital function in each clock cycle.

另一个主要优点是元素之间的延迟，这不再局限于时钟周期。
Another major advantage is the delay between elements, which is no longer limited to clock cycles.

位PWM分辨率可对应提供256个不同的亮度电平，相应的PWM周期由256个时钟周期组成。
With an 8-bit PWM resolution, 256 different intensity levels can be provided and the corresponding PWM period consists of 256 clock cycles.

附注：CEXn输入信号必须保持高电平或低电平至少两个系统时钟周期，以保证能够被硬件识别。
Note: The CEXn input signal must remain high or low for at least 2 system clock cycles in order to be valid.

通过串口读取完整的冷端补偿热电偶温度，需要14个时钟周期。
A complete serial-interface read of the cold-junction compensated thermocouple temperature requires 14 clock cycles.

这意味着它的访问两次为您的处理器时钟周期的每一个。
That means it's accessed twice for each one of your processor's clock cycles.

现代微处理器往往具有相当长的流水线，因此误预测延迟在10到20个时钟周期之间。
Modern microprocessors tend to have quite long pipelines so that the misprediction delay is between 10 and 20 clock cycles.

附注：CEXn输入信号必须保持高电平或低电平至少两个系统时钟周期，以保证能够被硬件识别。
Note: The CEXn input signal must remain high or low for at least 2 system clock cycles to be recognized by the.

这些512位矢量指令每个时钟周期可以执行32个双精度浮点运算或64个单精度浮点运算。
These 512-bit vector instructions can execute 32 double precision or 64 single precision floating-point operations per clock cycle.

因此，RISC架构需要更多RAM，但每个时钟周期总是执行一条指令以进行可预测的处理，这对于流水线操作非常有用。
Thus, RISC architecture requires more RAM but always executes one instruction per clock cycle for predictable processing, which is good for pipelining.

当我们提到时钟周期时，我们就是指波特率。
When we refer to a clock cycle, in the context of serial, we mean the baud rate.

IntelCPU是“四芯的”，也就是它们每个时钟周期发送4条指令。
Intel CPUs are"quad pumped", meaning they send 4 instructions per clock cycle.

所以在AMDCPU上400MHz的FSB是由潜在的200MHzFSB每个时钟周期发送2条指令组成的。
So an FSB of 400MHz on an AMD CPU is comprised of an underlying 200MHz FSB sending 2 instructions per clock cycle.

本文介绍基于RISC-V的SweRV内核，该内核基于经典的五级RISC-V流水线，每个时钟周期最多允许两条指令。
This article introduces the RISC-V-based SweRV core, which builds on the classic five-stage RISC-V pipeline and allows up to two instructions per clock cycle.

位处理器有能力快速执行复杂任务，每个时钟周期还能发送更多的数据。
A 32-bit processor is able to perform complex tasks quickly, because it can send more data per clock cycle.

该计数器每个时钟周期会递增一次，两个时钟周期会溢出，故每个周期会从0转换到1，再从1转换到0。
This counter will increment once for every clock cycle and takes two clock cycles to overflow, so every cycle it will alternate between a transition from 0 to 1 and a transition from 1 to 0.

在Silvermont架构的处理器上，每个指令花费1472时钟周期，不论操作数大小；在IvyBridge架构的处理器上，花费117时钟周期。
On the Silvermont microarchitecture processors, each of the instructions take around 1472 clock cycles, regardless of the operand size; and on Ivy Bridge processors RDRAND takes up to 117 clock cycles.

寄存器是最快的内存形式，每个时钟周期都可以访问（也就是说，2.0GHz的处理器每秒可以访问寄存器20亿次）。
Registers are the fastest form of memory, accessible every single clock cycle(that is, a 2.0 GHz processor can access registers two billion times a second).

简单地说，没有晶振，就没有时钟周期，没有时钟周期，就无法执行程序代码，单片机就无法工作。
Simply put, without a crystal oscillator, there is no clock cycle, no clock cycle, the program code cannot be executed, and the microcontroller cannot work.