Examples of using Clock cycles in English and their translations into Chinese
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The pins of Port 1 are sampled every clock cycle.
They simply send more instructions in every clock cycle.
只是在每个时钟周期中发送了更多的指令。They simply send more instructions in every clock cycle.
他们只是在每个时钟周期中发送了更多的指令。Solely on clock cycle timing.
只基于时钟周期定时。What this means is that two transfers occur every clock cycle.
但是，这意味着每个传输需要两个时钟周期。Thus length of bus cycle in 8086 is four clock cycle.
的基本总线周期由4个时钟周期组成。You can read a C program and"see" every clock cycle.
你可以阅读一个C程序，“看到”每个时钟周期。The pins of Port 1 are sampled every clock cycle.
端口1的管脚每个时钟周期采.This concept enables instructions to be executed in every clock cycle.
这个概念实现了每个时钟周期执行的指令。Internal pipelined operation; column address can be changed every clock cycle.
内部数据流水线操作，列地址可在每个时钟周期里改变.Without knowing the clock cycle times, it is impossible to state if one set of numbers is"faster" than another.
如果不知道时钟周期的时间，就不可能了解一组数字是否比另一组数字更快。The clock period is the time interval to repeat one clock cycle, usually measured in nanoseconds(nsec).
时钟周期就是时钟循环重复一次的时间间隔，通常用ns度量。Assume it has a 15-stage pipeline and can issue four instructions every clock cycle.
假设该芯片有一个15步的工作流程，每个时钟周期可以发送4条指令。In this architecture, a single CPU overlaps fetching, decoding and executing instructions to process one instruction each clock cycle.
在这种架构中，一个CPU交替处理指令的读取、解码和执行，每个时钟周期处理一条指令。For example, DDR3-2000 memory has a 1000 MHz clock frequency, which yields a 1 ns clock cycle.
举例来说，DDR3-2000内存的时钟频率是1000MHz，其时钟周期为1ns。Assume it has a 15-stage pipeline and can issue four instructions every clock cycle.
假设它有一个15-stage的pipeline，每个时钟周期可以发出四条指令。Our design allows the circuit to be rapidly morphed and reconfigured to perform a desired digital function in each clock cycle.
然而，他们的设计可以让电路可以迅速转变且重新配置，在每个时钟周期内完成特定的数字功能。In this case, it appears as if one instruction completes every clock cycle.
这样，表面看起来在每个时钟周期内即可执行完一条指令。Additionally, data can be updated(e.g., based on a clock cycle) and/or output to other devices for further processing.
另外，数据可以被更新（例如，基于一个时钟周期）和/或输出到其他装置上用于进一步处理。In the case of DDR(Dual Data Rate), 4-bit are transferred during a half clock cycle, i.
在DDR(双数据速率)模式下，4-bit传输可以在半个时钟脉冲周期内完成…….
