系统时钟 - 翻译成英语

• system clock
• system timing

在 中文 中使用 系统时钟 的示例及其翻译为 英语

附注：CEXn输入信号必须保持高电平或低电平至少两个系统时钟周期，以保证能够被硬件识别。
Note: The CEXn input signal must remain high or low for at least 2 system clock cycles in order to be valid.

卡中芯片的射频接口模块由此信号产生出电源电压、复位信号及系统时钟，使芯片“激活”；.
The RF interface module of the card chip generates the power voltage, the reset signal and the system clock, The chip"activated";

定时器3的时钟可以由系统时钟，系统时钟除以12，或外部振荡器.
Timer 3 may be clocked by the system clock, the system clock divided by 12, the external oscillator source.

收发信机114还包括信号检测器236和系统时钟电路238。
The transceiver 114 also includes a signal detector 236 and a system clock circuit 238.

可以使用三种不同的时钟源来驱动系统时钟(SYSCLK)：.
Three different clock sources can be used to drive the system clock(SYSCLK).

附注：CEXn输入信号必须保持高电平或低电平至少两个系统时钟周期，以保证能够被硬件识别。
Note: The CEXn input signal must remain high or low for at least 2 system clock cycles to be recognized by the.

能够同时运行两个系统时钟的能力也有助于减少太阳能电池板安装时出现的问题。
The ability to run two system clocks simultaneously also helps reduce problems with solar panel installation.

内部振荡器仍可产生系统时钟时，外部振荡器驱动定时器1。
Internal oscillator may still generate the system clock when the external oscillator is driving Timer 1.

一个很小的系统时钟错误积累起来就可能拖延14小时，造成跟踪系统失去准确度。
A small timing error in the system's clock accumulated to the point that after 14 hours, the tracking system was no longer accurate.

初始系统时钟是从硬件时间计算得来，计算时会考虑/etc/adjtime的设置。
The initial value of the system clock is calculated from the hardware clock, dependent on the contents of/etc/adjtime.

数据按下降沿到下降沿测量，每个脉冲的持续时间与系统时钟周期数相关。
The data is measured as falling edge to falling edge, and the duration of each pulse is related to the number of system clock ticks.

时钟丢失检测器(MCD)是由系统时钟触发的单稳态电路。
The Missing Clock Detector(MCD) is a one-shot circuit that is triggered by the system clock.

基于历史先例，PRNG的种子通常是参照系统时钟生成的。
Based on historical precedent, seeds for number generators are usually produced based on the system clock.

缺失时钟探测器(MCD)是由系统时钟触发的单触法电路。
The Missing Clock Detector(MCD) is a one-shot circuit that is triggered by the system clock.

存储在系统设置程序中的时间或日期与系统时钟不符。
The time or date stored in the system setup program does not match the system clock.

允许改变系统时钟.
Changing the system clock.

然后检查系统时钟。
Checking the system clock.

系统时钟除以4.
System clock divided by 4.

VxWorks系统时钟使用问题.
Provides the VxWorks system clock.

定义为选主系统时钟.
Selected as system clock.